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| DM74LS259 8-Bit Addressable Latches August 1986 Revised March 2000 DM74LS259 8-Bit Addressable Latches General Description These 8-bit addressable latches are designed for general purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and active-high decoders or demultiplexers. They are multifunctional devices capable of storing single-line data in eight addressable latches, and being a 1-of-8 decoder or demultiplexer with active-high outputs. Four distinct modes of operation are selectable by controlling the clear and enable inputs as enumerated in the function table. In the addressable-latch mode, data at the datain terminal is written into the addressed latch. The addressed latch will follow the data input with all unaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latches, the enable should be held HIGH (inactive) while the address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output will follow the level of the D input with all other outputs LOW. In the clear mode, all outputs are LOW and unaffected by the address and data inputs. Features s 8-Bit parallel-out storage register performs serial-to-parallel conversion with storage s Asynchronous parallel clear s Active high decoder s Enable/disable input simplifies expansion s Direct replacement for Fairchild DM9334 s Expandable for N-bit applications s Four distinct functional modes s Typical propagation delay times: Enable-to-output Data-to-output Clear-to-output s Fan-out IOL (sink current) s Typical ICC 22 mA 8 mA IOH (source current) -0.4 mA 18 ns 16 ns 17 ns Address-to-output 21 ns Ordering Code: Order Number DM74LS259M DM74LS259WM DM74LS259N Package Number M16A M16B N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. (c) 2000 Fairchild Semiconductor Corporation DS006418 www.fairchildsemi.com DM74LS259 Connection Diagram Function Table Inputs Clear H H L L E L H L H Output of Addressed Latch D Qi0 D L Each Other Output Qi0 Qi0 L L Addressable Latch Memory 8-Line Demultiplexer Clear Function Latch Selection Table Select Inputs C L L L L H H H H B L L H H L L H H A L H L H L H L H Latch Addressed 0 1 2 3 4 5 6 7 H = HIGH Level L = LOW Level D = the Level of the Data Input Qi0 = the Level of Qi (i = 0, 1,...7, as Appropriate) before the Indicated Steady-State Input Conditions Were Established. www.fairchildsemi.com 2 DM74LS259 Absolute Maximum Ratings(Note 1) Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0C to +70C -65C to +150C Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the "Electrical Characteristics" table are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL tW tSU tH TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Pulse Width (Note 5) Setup Time Hold Time (Note 2)(Note 3)(Note 5) Free Air Operating Temperature Enable Clear Data Data Select 15 15 15 15 2.5 2.5 0 70 Parameter Min 4.75 2 0.8 -0.4 8 Nom 5 Max 5.25 Units V V V mA mA ns ns ns C (Note 2)(Note 3)(Note 4)(Note 5) Select Note 2: The symbols (, ) indicate the edge of the clock pulse used for reference: for rising edge, for falling edge. Note 3: Setup and hold times are with reference to the enable input. Note 4: The select-to-enable setup time is the time before the HIGH-to-LOW enable transition that the select must be stable so that the correct latch is selected and the others not affected. Note 5: TA = 25C and VCC = 5V. Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOS ICC Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Enable Short Circuit Output Current Supply Current Conditions VCC = Min, II = -18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max, VI = 7V VI = 10V VCC = Max, VI = 2.7V VCC = Max, VI = 0.4V VCC = Max, VI = 0.4V VCC = Max (Note 7) VCC = Max (Note 8) -20 22 2.7 3.4 0.35 0.25 0.5 0.4 0.1 20 -0.4 -0.8 -100 36 mA A mA mA mA Min Typ (Note 6) Max -1.5 Units V V V Note 6: All typicals are at VCC = 5V, TA = 25C. Note 7: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 8: ICC is measured with all inputs at 4.5V, and all outputs OPEN. 3 www.fairchildsemi.com DM74LS259 Switching Characteristics at VCC = 5V and TA = 25C From (Input) Symbol Parameter To (Output) Min tPLH tPHL tPLH tPHL tPLH tPHL tPHL Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time HIGH-to-LOW Level Output Enable to Output Enable to Output Data to Output Data to Output Select to Output Select to Output Clear to Output CL = 50 pF RL = 2 k Max 38 32 35 30 41 38 36 ns ns ns ns ns ns ns Units www.fairchildsemi.com 4 DM74LS259 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M16B 5 www.fairchildsemi.com DM74LS259 8-Bit Addressable Latches Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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